Electronic systems such as digital clocks or circuits for synthesizing analog frequencies typically require a clock signal having a lower jitter in its output. Clock jitter refers to fluctuation in the phase of a signal and also encompasses phase noise. A crystal reference may be utilized to provide a lower jitter, however crystals are relatively expensive and difficult to integrate with an integrated circuit. A phase-locked loop (PLL) may be utilized to generate a clock signal, however the output of a phase-locked loop generally have an unacceptable amount of jitter for certain applications. Jitter in a PLL may be reduced by designing the PLL with a higher precision loop filter, a higher precision phase comparator, or a higher-order feedback network. However, these techniques for reducing PLL jitter are disadvantageous in that a larger area on an integrated circuit is required, and lock-in time, circuit complexity, and noise sensitivity are increased.